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| ver1.0 1 ld1022 16 channel constant current led driver ld1022 16 channel constant current led driver ver. 1.0 / mar. 2009 this document is a general product descriptio n and is subject to change without notice. ldt inc. does not assume any responsibility for use of circuits described. ld1022 16 channel constant current led driver
ver1.0 2 ld1022 16 channel constant current led driver ld1022 revision history ' j s t u 7 f s t j p o 5 s b o t g f s % b u f $ p o u f o u t 7 f s t j p o ver1.0 3 ld1022 16 channel constant current led driver description ld1022 is designed for led displays with output current gain control. ld1022 contains a serial buffer and data latches, which convert serial input data into parallel output format. at ld1022 output stage, sixteen regulated current ports are designed to provide constant current sinks for driving leds within a wide range of vf variations. features ? 16 constant current output channels ? constant current output range: 5ma ~ 70ma ? output current adjustable through an external resistor ? 8-bit programmable output current control ? output current accuracy: - between channels: ? 1.0% (25ma < iout < 70ma) ? 1.3% (3ma < iout < 24ma) - between ics : ? 3.0% ? 25mhz clock frequency ? fast response of output current, pulse width: 50ns ? 3v ~ 5v supply voltage ? pb-free package: ssop24 (150) with two kinds of pin assignments pin connection (top view) gnd sdi clk le out0 out1 out2 out3 out4 out5 out6 out7 vdd r-ext sdo oeb out15 out14 out13 out12 out11 out10 out9 out8 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 block diagram ordering information ? $ u p ? $ 4 0 1 - % 4 1 ? $ u p ? $ 4 4 0 1 - % 4 4 5 " 1 " $ , " ( & 1 " 3 5 / 6 . # & 3 ver1.0 4 ld1022 16 channel constant current led driver timing diagram 1 2 3 4 13 14 15 16 clock sdi on off on off on off on off on off le oeb out0 out1 out2 out14 out15 sdo normal mode truth table d n-12 off d n+4 h x x d n-13 dn+2 ?dn-5 ... dn-13 d n+3 l x x d n-13 dn+2 ?dn-5 ... dn-13 d n+2 l h ? ? d n-14 no change d n+1 l l x d n-15 dn ?dn-7 ... dn-15 d n l h ? ? sdo out0 ? out7 ? out15 sdi oe le clk ? when le is high at the rising edge of the 16 th clk, data from sdi will la tch into the 16-bit output latch at the falling edge of le the operation of is independent to the interface signals (clk, sdi, sdo), an unstable period of t plh2 or t phl2 will appear at when new 16-bit data is latched with valid le (see timing diagram for normal mode) new data appear at sdo w ill have delay time of t plh or t phl from rising edge of clk only ver1.0 5 ld1022 16 channel constant current led driver terminal description equivalent circuit of inputs and outputs oeb terminal vdd oeb gnd 2. le terminal vdd le gnd 3. clk, sdi terminal vdd gnd 4. sdo terminal vdd (data) gnd clock, sdi sdo 7 t v q q m z w p m u b h f u f s n j o b m 7 % % * o q v u u f s n j o b m v t f e u p d p o o f d u b o f y u f s o b m s f t j t u p s g p s t f u u j o h v q b m m p v u q v u d v s s f o u 3 & 9 5 4 f s j b m e b u b p v u q v u u p u i f g p m m p x j o h 4 % * p g o f y u e s j w f s * $ 4 % 0 0 v u q v u f o b c m f u f s n j o b m 8 i f o b d u j w f m p x u i f p v u q v u e s j w f s t b s f f o b c m f e x i f o i j h i b m m p v u q v u e s j w f s t b s f u v s o f e 0 ' ' c m b o l f e 0 & # $ p o t u b o u d v s s f o u p v u q v u u f s n j o b m t * 0 6 5 _ * 0 6 5 _ % b u b t u s p c f j o q v u u f s n j o b m 4 f s j b m e b u b j t m b u d i f e b u u i f g b m m j o h f e h f p g - & " m t p b d p o u s p m t j h o b m j o q v u g p s $ v s s f o u " e k v t u n p e f - & $ m p d l j o q v u u f s n j o b m g p s e b u b t i j g u p o s j t j o h f e h f $ - , 4 f s j b m e b u b j o q v u u p u i f 4 i j g u 3 f h j t u f s 4 % * ( s p v o e u f s n j o b m g p s d p o u s p m m p h j d b o e d v s s f o u t j o l ( / % ' v o d u j p o 1 j o / b n f 1 j o / p ver1.0 6 ld1022 16 channel constant current led driver maximum ratings (ta = 25 o c unless otherwise noted) ma 1120 i gnd gnd terminal current w 1.67 p d sop power dissipation ( on pcb, ta = 25 ? ) 1.48 ssop ssop sop mhz 25 f clk clock frequency v -0.4 ~ v dd + 0.4 v in input voltage ma 80 i out output current v -0.5 ~ 7.0 v out output voltage v 0 ~ 7.0 v dd supply voltage 85 ? -40 ~ 85 t opr operation temperature ? /w 75 r th(j-a) thermal resistance ( on pcb, ta = 25 ? ) ? -55 ~ 150 t stg storage temperature unit rating symbol characteristic ver1.0 7 ld1022 16 channel constant current led driver electrical characteristics (ta = 25 o c unless otherwise noted) w tbd ta=85 c pd power dissipation mhz 25.0 cascade operation fclk clock frequency ns 15 th(ca) hold time for le ns 15 tsu(ca) setup time for le ns 20 current adjust mode vdd=4.5 ~ 5.5v tw(clk) clk pulse width ns 15 th(l) hold time for le ns 15 tsu(l) setup time for le ns 10 th(d) hold time for sdi ns 5 tsu(d) setup time for sdi ns 20 tw(clk) clk pulse width ns 50 tw(oe) pulse width ns 20 normal mode vdd=4.5 ~ 5.5v tw(l) le pulse width v 0.3*vd d -0.3 clk,, le and sdi vil v vdd+ 0.3v 0.8vdd clk, , le and sdi vih input voltage ma 1.0 sdo iol ma -1.0 sdo ioh ma 50 3 refer to dc test circ uit iout output current v 5.5 ~ vds output voltage v 5.5 5.0 3.0 vdd supply voltage unit max. typ. min. condition symbol characteristic ver1.0 8 ld1022 16 channel constant current led driver switching characteristics (v dd =5.0v) (ta = 25 o c unless otherwise noted) ns 20 15 tof output fall time of iout ns 20 15 tor output rise time of iout ns 500 tf** maximum clk fall time ns 500 tr** maximum clk rise time ns 10 tfall setup time for le (current adjust mode) ns 10 tsu(l) setup time for le (normal mode) ns 10 th(l) hold time for le (normal mode) ns 200 tleoe le ? delay time ns 50 twh(oe) ns 50 tw(oe) ns 20 tw(l) le ns 20 tw(clk) clk pulse width ns 20 15 tphl clk - sdo ns 45 40 tphl3 - ns 150 100 tphl2 le - ns 150 100 tphl1 clk - propagation delay time (?h? to ?l?) ns 20 15 tplh clk - sdo ns 45 40 tplh3 - ns 100 50 tplh2 le - ns 100 50 vdd=5.0 v vds=1.5 v vih=vdd vil=gnd r-ext=360 ? vl=4.0 v rl=50 ? cl=10 pf tplh1 clk - propagation delay time (?l? to ?h?) unit max. typ. min. condition symbol characteristic ver1.0 9 ld1022 16 channel constant current led driver dc characteristic test circuit v dd i dd ld1022 out0 out15 sdo i out r-ext gnd iref i ih i il v ih v il ac characteristic test circuit signal generator v ih v il c l v l oeb le sdi r l c l v dd ld1022 out0 out15 sdo r-ext gnd oeb le sdi clock clock r l rext rext i oh i ol ver1.0 10 ld1022 16 channel constant current led driver timing waveform t plh 2, t phl 2 clk sdi sdo _____ outn le __ oe t w(clk ) t su(d ) t h(d) t plh , t phl t plh 1, t phl 1 low = output is enabled high = output off low = output on normal mode t su (l) t h (l) t w (l) ver1.0 11 ld1022 16 channel constant current led driver t w(clk) t su(ca) t h(ca) 16 clk pulses clk le __ oe t leoe 1 2 16 17 t fall 15 clk pulses * the falling edge of le should be appeared before t fall entering current adjust mode ver1.0 12 ld1022 16 channel constant current led driver adjusting output current the output current is determined by an external resistor. the relationship between i out and r ext is as follows; i out [a] = {1.16/(90+r ext )} * 22 when vdd = 5v when vdd = 3.3v i out [a] = {1.16/(90+r ext )} * 21 vdd = 5.0v ( ? ) 3 f y u * p v u 3 f y u * p v u n " ver1.0 13 ld1022 16 channel constant current led driver current adjust mode during current adjust mode, the system controller should send 16bit of data including the 8-bit current adjust code (bit0 to bit7) to the sdi pin. once le holds high for 16 clk cycles, sampling at every rising edge of clk, bct5028 will re-direct the contents stored in the shift register to a 16-bit configuration latch cr [15:0] rather than the 16-bit output latch in a normal mode. pin oe always enables the output port no matter bct5028 enters a current adjust mode or not. 1. configuration register (cr [15:0]) current adjust code c j u c j u c j u c j u c j u c j u c j u c j u c j u c j u c j u c j u c j u c j u c j u c j u 255 1 1 1 1 1 1 1 1 254 0 1 1 1 1 1 1 1 253 1 0 1 1 1 1 1 1 - - - - - - - - - - - - - - - - - - 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit setting bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 2. current gain table default setting: ffh iout = [bit_setting + 72] / [18*rext] where rext: external resistor bit setting: current value for example: example 1: if r-ext =360 ohm; cr<7:0>=00h will provide 11.11ma cr<7:0>=ffh will provide 50.46ma example 2: if r-ext =1000 ohm; cr<7:0>=00h will provide 4.00ma cr<7:0>=ffh will provide 18.17ma ver1.0 14 ld1022 16 channel constant current led driver constant output current the ld1022 provides a constant current output characteristics for led display application. the pin to pin deviation is max +/- 1.5% and chip to chip deviation is max +/- 3%. when vdd = 5.0v 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 0 6 5 $ v s s f o u ? ? ? ? ? ? i out (ma) ver1.0 15 ld1022 16 channel constant current led driver led supply voltage( vled ) !? !? v led vf ld1022 v out !? !? v led vf ld1022 v out r l it is very important to select the proper value of load resistor( rl ). because the optimal vout value guarantees the constant output current and long life time of led driver ic without over power consumption. for example, let?s calculate the load resistor value at vled=5v, iout=20ma, led forward voltage(vf)=3v. 1) the full current of ld1022 = 20ma x 16 (channels) = 320ma 2) the power consumption is 320ma x vout voltage. - when vout = 1v, the power consumption is 320mw. - when vout= 2v, the power consumption is 640mw. therefore, the load resistor (rl) = (vled ? vout? vf) / iout = (5v ? vout ? 3v) / 20ma = 50 ? (when vout = 1v) ver1.0 16 ld1022 16 channel constant current led driver package power dissipation( pd ) the ld1022 provides many package types such as 24-sop package and 24-ssop package. the maximum allowable package power dissipation is determined as pd(max) = (tj ? ta) / r_theta_ja. when 16 output channels are turned on simultaneously, the actual power dissipation of package is pd(act) = (idd x vdd) + (iout x duty x vout x 16). therefore, to keep that pd(act) is less than pd(max). the maximum allowable output current as a function of duty cycle is: * p v u w t % v u z 4 0 1 % v u z * p v u n " 5 b 5 b 5 b 5 b ( r_theta_ja = 75c/w ) * p v u w t % v u z 4 4 0 1 % v u z * p v u n " 5 b 5 b 5 b 5 b ( r_theta_ja = 85c/w ) iout = {[(tj ? ta) / r_theta_ja] ? (idd x vdd)} / vout / duty / 16 where tj =150c 1 b d l b h f 1 p x f s % j t t j q b u j p o " n c j f o u 5 f n q f s b u v s f $ 1 p x f s % j t t j q b u j p o 8 4 0 1 4 4 0 1 ver1.0 17 ld1022 16 channel constant current led driver application circuit1 four chips are connected in cascade configuration, data are progra mmed in current adjust mode then follow by normal mode. example on data written in sequence ver1.0 18 ld1022 16 channel constant current led driver application circuit 2 (16x2 static type) data & control signal connection for 16x2 static type application ld1022 out0 out15 r-ext out7 clock sdo v dd oeb le sdi out0 out15 r-ext gnd gnd out7 clock sdo oeb le sdi ld1022 sdi oeb le clock v dd v dd vdd vdd v led = 5v d00 d07 d015 i 0 i 7 i 15 r l r l r l v led = 5v d10 d17 d115 i 0 i 7 i 15 r l r l r l ver1.0 19 ld1022 16 channel constant current led driver timing diagram for ap plication circuit 2 (16x2 static type) clock le sdi oeb d115~d10 d015 ~ d00 ( 1st data ) d115~d10 d015 ~ d00 (2nd data) clock le sdi oeb display on display off 1st data display 2nd d115~d10 d015 ~ d00 ( 1st data ) d115~d10 d015 ~ d00 (2nd data) 1st data display 2nd 16 clocks 16 clocks 16 clocks 16 clocks 16 clocks 16 clocks 16 clocks 16 clocks timing diagram for applicat ion circuit 2 (16x2 stat ic type) : another case ver1.0 20 ld1022 16 channel constant current led driver controller r vled = 5v r l r l r l vdd vdd r l r l r l r l r l r l pnp pnp r 4 r 5 q15 pnp pnp r 4 r 5 q1 pnp pnp r 4 r 5 q0 d00 d01 d015 d10 d11 d115 d150 d151 d1515 data clk stb esb application circuit 2 (16x16 dynamic type) sdi clock le oeb vdd sdo r-ext gnd out0 out1 out15 ld1022 s0 s1 s15 data & control signal connection for 16x16 dynamic type application ver1.0 21 ld1022 16 channel constant current led driver clock le s0 sdi d015 ~ d00 (1st display data) oeb d115 ~ d10 ( 2nd display data) s1 s15 d1515 ~ d150 (16th display data) row driver non overlap time (1st display data) (2nd display data) (16th display data) 16 clocks 16 clocks 16 clocks timing diagram for ap plication circuit 2 (16x16 dynamic type) ver1.0 22 ld1022 16 channel constant current led driver r vled = 5v r l r l vdd vdd r l r l pnp pnp r 4 r 5 q15 pnp pnp r 4 r 5 q0 s0 s15 d0000 d0015 d0150 d01515 r l r l d1000 d1015 vdd r r l r l d11515 d1150 data clk stb esb controller sdi clock le oeb vdd sdo r-ext gnd out0 out15 ld1022 sdi clock le oeb vdd sdo r-ext gnd out0 out15 ld1022 application circuit 3 (32x16 dynamic type) data & control signal connection for 32x16 dynamic type application ver1.0 23 ld1022 16 channel constant current led driver clock le s0 sdi d1015 ~ d1000, d0015 ~ d0000 (1st display data) oeb s15 (1st display data) (16th display data) 32 clocks 32 clocks d11515 ~ d1150, d01515 ~ d0150 (16th display data) timing diagram for ap plication circuit 3 (32x16 dynamic type) ver1.0 24 ld1022 16 channel constant current led driver ld1022-sp (sop 24) package information ver1.0 25 ld1022 16 channel constant current led driver ld1022-ss (ssop 24) ver1.0 26 ld1022 16 channel constant current led driver the products listed herein are designed for ordinary electronic applications, such as electrical applications, audio-visual equipment, communications devices and so on. hence, it is advisable that the devices should not be used in medical instrument, surgical implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention equipment and the like. misusing those products ma y directly or indirectly endanger human life, or cause injury and property loss. ldt will not take any responsibiliti es regarding the misusage of the produc ts mentioned above. anyone who purchases any products described herein with the above-me ntioned intention or with such misused application should accept full responsibility and inde mnify. ldt and its distributors a nd all their officers and employees shall defend jointly and severally against any and all clai ms and litigation and all damages, cost and associated with such intention and manipulation. |
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